View UPD17P203AGC-001-3BH_1672082.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description m pd17p203a and m pd17p204 are variations of m pd17203a and m pd17204 respectively and are equipped with a one-time prom instead of an internal mask rom. m pd17p203a and m pd17p204 are suitable for evaluating a program when developing m pd17203a and m pd17204 systems respectively because the program can be written by the user. when reading this document, also refer to the m pd17203a and m pd17204 data sheets. features ? 17k architecture: general-purpose register format ? pin-compatible (except for prom programming function): m pd17p203a with m pd17203a m pd17p204 with m pd17204 ? internal one-time prom: 4096 x 16 bits ( m pd17p203a) 7936 x 16 bits ( m pd17p204) ? static ram: 16 kbits ( m pd17p203a) 8 kbits ( m pd17p204) ? power supply voltage: 2.9 to 5.5 v (at t a = C20 to +75 c, f x = 4mhz) 2.0 to 5.5 v (at t a = C20 to +75 c, f xt = 32khz) the features of each product is shown in the following table: m pd17p203a-001 m pd17p204-001 provided item pull-up resistor of reset pin pull-up resistor of p0a and p0b pins main clock oscillator circuit subclock oscillator circuit m pd17p203a-002 m pd17p204-002 not provided provided not provided m pd17p203a-003 m pd17p204-003 not provided provided m pd17203a m pd17204 on request (mask option) m pd17p203a and m pd17p204 are different from m pd17203a and m pd17204 respectively in the power supply voltage and the operating ambient temperature. therefore, use m pd17p203a and m pd17p204 only for the system evaluation. mos integrated circuit m pd17p203a, 17p204 4-bit single-chip microcontroller with static ram and 3-channel timer for infrared remote controller the mark h shows major revised points. the information in this document is subject to change without notice. document no. ic-2851a (o. d. no. ic-8303b) date published june 1995 p printed in japan this document explains m pd17p204 as a typical product where no specification is made. 1992 data sheet
m pd17p203a, 17p204 2 ordering information part number package m pd17p203agc-001-3bh 52-pin plastic qfp (14 14 mm) m pd17p203agc-002-3bh 52-pin plastic qfp (14 14 mm) m pd17p203agc-003-3bh 52-pin plastic qfp (14 14 mm) m pd17p204gc-001-3bh 52-pin plastic qfp (14 14 mm) m pd17p204gc-002-3bh 52-pin plastic qfp (14 14 mm) m pd17p204gc-003-3bh 52-pin plastic qfp (14 14 mm)
3 m pd17p203a, 17p204 pin configuration (top view) (1) normal operation mode ampinC : operational amplifier input ampout : operational amplifier output cmpin+ : comparator input cmpout : comparator output gnd 0 -gnd 5 : ground int : external interrupt input led : remote controller transmission output indicator p0a 0 -p0a 3 : i/o port 0a p0b 0 -p0b 3 : i/o port 0b p0c 0 -p0c 3 : i/o port 0c p0d 0 -p0d 3 : i/o port 0d p1a 0 -p1a 3 : i/o port 1a p1b 0 -p1b 3 : i/o port 1b p1c 0 -p1c 3 : i/o port 1c rem : remote controller transmission output reset : reset input sck : serial clock input/output si : serial data input so : serial data output tm0in : timer 0 input tm0out : timer 0 output tm1out : timer 1 output tm2out : timer 2 output v dd : power supply v reg : voltage regulator output v ref : reference voltage output v xram : static ram (xram) power supply wdout : overrun detection output x in , x out : main clock oscillation use xt in , xt out : subclock oscillation use p1c 3 led p0d 2 gnd 1 p1c 2 /si p1c 1 /so p1c 0 /sck p1b 3 /tm2out p1b 2 /tm1out p1b 1 /tm0out p1b 0 p1a 3 p1a 2 p1a 1 p1a 0 p0d 3 ampin gnd 2 ampout v ref cmpin+ gnd 3 cmpout tm0in int p0a 0 p0a 1 p0a 2 rem v xram v dd x in x out gnd 0 reset wdout xt in xt out v reg gnd 5 p0d 1 p0d 0 p0c 3 p0c 2 p0c 1 gnd 4 p0c 0 p0b 3 p0b 2 p0b 1 p0b 0 p0a 3 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 m pd17p203agc-001-3bh m pd17p203agc-002-3bh m pd17p203agc-003-3bh m pd17p204gc-001-3bh m pd17p204gc-002-3bh m pd17p204gc-003-3bh
m pd17p203a, 17p204 4 (2) prom programming mode d 2 gnd 1 d 3 (l) gnd 2 (open) (l) gnd 3 (open) (l) v pp (l) gnd v dd clk (open) (l) gnd 5 d 1 d 0 d 7 d 6 d 5 d 4 md 3 md 2 md 1 md 0 (l) 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 11 12 13 gnd 4 (open) (l) gnd 0 (open) (open) (l) clk : prom clock input d0-d7 : prom data i/o gnd, gnd 0 -gnd 5 : ground md0-md3 : prom mode selection v dd : power supply v pp : program power supply caution those enclosed in parentheses indicate the processing of the pins not used in prom programming mode. l : ground these pins through a resistor (470 w ). open : do not connect anything to these pins. m pd17p203agc-001-3bh m pd17p203agc-002-3bh m pd17p203agc-003-3bh m pd17p204gc-001-3bh m pd17p204gc-002-3bh m pd17p204gc-003-3bh
5 m pd17p203a, 17p204 block diagram p0a 0 p0a 1 p0a 2 p0a 3 p0b 0 /md0 p0c 0 /d4 p1b 0 p1b 1 /tm0out p1b 2 /tm1out p1b 3 /tm2out serial i/o p1c p0a p0b p0c p1b timer0/ counter ram 336 4 bits system reg. program counter stack instruction decoder v reg v dd v xram gnd 2 gnd 3 gnd 4 cpu clock clock stop cpu clock int/v pp interrupt controller reset wdout xt in power supply circuit alu watch timer divider main clock subclock rf p0d p1a 0 p1a 1 p1a 2 p1a 3 p1a timer1/ counter timer2/ counter xram 4096 4 bits ( pd17p203a) 2048 4 bits ( pd17p204) m m 5 12 bits ( pd17p203a) 7 13 bits ( pd17p204) m m 4096 16 bits ( pd17p203a) 7936 16 bits ( pd17p204) m m one time prom remote control receiver remote control transmitter rem led cmpout tm0in cmpin + ampout ampin gnd 5 v ref gnd 0 gnd 1 xt out x in /clk x out p0b 1 /md1 p0b 2 /md2 p0b 3 /md3 p0c 1 /d5 p0c 2 /d6 p0c 3 /d7 p0d 0 /d0 p0d 1 /d1 p0d 2 /d2 p0d 3 /d3 p1c 0 /sck p1c 1 /so p1c 3 p1c 2 /si
m pd17p203a, 17p204 6 contents 1. pin functions ..................................................................................................................... 7 1.1 normal operation mode ..................................................................................................... 7 1.2 prom programming mode ................................................................................................... 9 1.3 pin i/o circuits .......................................................................................................................... 9 1.4 processing of unused pins ................................................................................................ 12 1.5 notes on using reset and int pins ................................................................................. 13 2. differences between mask rom products and one-time prom products .............................................................................................................................. 14 3. one-time prom (program memory) writing, reading, and verification ............................................................................................................... 15 3.1 operation mode for writing, reading, and verification of program memory .......................................................................... 15 3.2 program memory write procedure ................................................................................ 16 3.3 program memory read procedure ................................................................................. 17 4. electrical specifications ............................................................................................. 18 5. package drawings ........................................................................................................... 23 6. recommended soldering conditions ...................................................................... 24 appendix a. microcontrollers for learning remote controller ............. 25 appendix b. development tools ..................................................................................... 26 h h
7 m pd17p203a, 17p204 1. pin functions 1.1 normal operation mode pin no. symbol function output format at reset outputs nrz signal in synchronization with infrared remote controller signal. remains low while remote control carrier is output outputs active-high infrared remote control signal supplies power to xram positive power connect 4-mhz ceramic oscillator for main clock oscillation ground inputs low-active system reset signal. while this pin remains low level, oscillation of main clock stops. pull-up resistor can also be connected by mask option ( m pd17p203a-001 and m pd17p204-001 only). outputs signal for detecting overrun. this pin outputs a low-level when an overflow in the watchdog timer or an overflow/underflow in the stack is detected. connect this pin to the reset pin. connect 32-khz crystal oscillator across these pins. when option not using subclock is selected, main clock is divided and is supplied to watch timer. outputs signal from voltage regulator for subclock oscillator circuit. connect external 0.1- m f capacitor. ground ground of operation amplifier inverted input of operational amplifier ground of operational amplifier output of operational amplifier outputs reference voltage of 1/2v dd . connect external 0.1- m f capacitor. non-inverted input of comparator. output of this comparator can be obtained from cmpout. ground of operational amplifier high-level output low-level output C C (oscillation stop) C C high impedance (oscillation) C C C input C output C input C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 led rem v xram v dd x in x out gnd 0 reset wdout xt in xt out v reg gnd 5 gnd 1 ampin- gnd 2 ampout v ref cmpin+ gnd 3 cmos push-pull cmos push-pull C C C C C n-ch open drain C C C C C C C C C C (1/2) h remark gnd 1 -gnd 3 are the ground pins of the operational amplifier. keep all these pins at the same potential to stabilize the operation of the operational amplifier.
m pd17p203a, 17p204 8 pin no. symbol function output format at reset comparator output. externally connect cmpout and tm0in when using microcontroller as teaching remote controller clock input to timer 0. input clock is sampled by internal clock and then input to envelope signal generator circuit, as well as to timer 0. by using timer 0 with timer 1, frequency of clock input to this pin can be measured. external interrupt signal input pin constitute 4-bit i/o port, which can be set in input or output mode in 4-bit units. pull-up resistor can be connected by mask option ( m pd17p203a-001, -002 and m pd17p204-001, -002 only). when one or more of these pins goes low in standby mode standby mode is released. constitute 4-bit i/o port, which can be set in input or output mode in 4-bit units. ground constitute 4-bit i/o port, which can be set in input or output mode in 4-bit units. constitute 4-bit i/o port, which can be set in input or output mode in bitwise. pull-up registor can be connected through program. port 1b or timer output ? p1b 0 -p1b 3 - 4-bit i/o port - can be set in input/output mode in bitwise - pull-up resistor can be connected through program ? tm0out-tm2out - timer output port 1c or serial interface i/o ? p1c 0 -p1c 3 - 4-bit i/o port - can be set in input/output mode in bitwise ? sck, so, si - sck : serial clock i/o - so : serial clock data output - si : serial clock data input output input input input input C input input input (p1b 0 -p1b 3 ) input (p1c 0 -p1c 3 ) C C C cmos push-pull n-ch open drain C n-ch open drain n-ch open drain n-ch open drain cmos push-pull 21 22 23 24 to 27 28 to 31 32 34 to 36 33 37 to 40 41 to 44 45 46 47 48 49 50 51 52 (2/2) cmpout tm0in int p0a 0 to p0a 3 p0b 0 to p0b 3 p0c 0 p0c 1 to p0c 3 gnd 4 p0d 0 to p0d 3 p1a 0 to p1a 3 p1b 0 p1b 1 / tm0out p1b 2 / tm1out p1b 3 / tm2out p1c 0 /sck p1c 1 /so p1c 2 /si p1c 3 caution for a standard products, note that standby mode is released when one or more of p0c and p0d pins goes high in standby mode.
9 m pd17p203a, 17p204 1.2 prom programming mode pin no. symbol function output format at reset ground positive power address updating clock input supplies program voltage. apply 12.5v to this pin selects prom programming mode 8-bit data i/o gnd gnd 0 gnd 5 gnd 1 gnd 2 gnd 3 gnd 4 v dd clk v pp md 0 to md 3 d 4 to d 7 d 0 to d 3 3 7 13 14 16 20 33 4 5 23 28 to 31 32, 34 to 36 37 to 40 C C C C C cmos push-pull C C input C input input 1.3 pin i/o circuits this section shows the i/o circuits of the m pd17p204 pins in simplified schematic diagrams. (1) p0a 0 -p0a 3 , p0b 0 /md0-p0b 3 /md3 output latch data output disable in p ut buffer p-ch n-ch v dd v dd pull-up resistor note note m pd17p203a-001, -002 and m pd17p204-001, -002 only.
m pd17p203a, 17p204 10 (2) p0c 0 /d4-p0c 3 /d7, p0d 0 /d0-p0d 3 /d3 (3) p1a 0 -p1a 3 , p1b 0 -p1b 3 /tm2out data n-ch input buffer output disable output latch data output disable n-ch in p ut buffer v dd p-ch data pull-up resistor output latch
11 m pd17p203a, 17p204 (4) p1c 0 /sck-p1c 3 (5) reset in p ut buffer pull-up resistor note v dd data output disable input buffer p-ch n-ch v dd v dd p-ch data pull-up resistor output latch note m pd17p203a-001 and m pd17p204-001 only
m pd17p203a, 17p204 12 1.4 processing of unused pins the following are recommended to process unused pins. table 1-1. processing of unused pins pin recommended connection int, tm0in connect to v dd or gnd p0a 0 -p0a 3 , p0b 0 -p0b 3 input: connect each pin to v dd through resistor output: open (high-level output) p0c 0 -p0c 3 , p0d 0 -p0d 3 input: connect each pin to v dd or gnd through resistor p1a 0 -p1a 3 , p1b 0 -p1b 3 output: open (low-level output) p1c 0 -p1c 3 input: connect each pin to v dd or gnd through resistor ouput: open led open rem open wdout connect to gnd x in x out connect to v dd xt in connect to gnd xt out connect to v reg ampinC connect to gnd or ampout ampout, cmpout open cmpin+ connect to gnd v ref open h
13 m pd17p203a, 17p204 1.5 notes on using reset and int pins (normal operation mode only) in addition to the functions shown in 1. pin functions , the reset and int pins also have a function to set a test mode (for ic testing) in which the internal operations of the m pd17p204 are tested. when a voltage higher than v dd is applied to either of these pins, the test mode is set. this means that, even during normal operation, the m pd17p204 may be set in the test mode if a noise exceeding v dd is applied. for example, if the wiring length of the reset or int pin is too long, noise superimposed on the wiring line of the pin may cause the above problem. therefore, keep the wiring length of these pins as short as possible to suppress the noise; otherwise, take noise preventive measures as shown below by using external components. ? connect diode with low v f between v dd ? connect capacitor between v dd and reset/int pin and reset/int pin h reset, int diode with low v f v dd v dd reset, int v dd v dd
m pd17p203a, 17p204 14 2. differences between mask rom products and one-time prom products the m pd17p203a and m pd17203 are identical in the cpu functions and internal hardware peripherals except for that the m pd17p204 is provided with a prom, which can be written by the user, in the place of the mask rom of the m pd17204. the only differences between the two microcontrollers are therefore the program memory and mask option. the relation between the m pd17p204 and m pd17204 is the same as the relation between the m pd17p203a and m pd17203. note that the m pd17p203a and m pd17p204 is slightly different from the m pd17203a and m pd17204 respectively in electrical characteristics, such as supply voltage and supply current. the following shows the differences between m pd17p203a and m pd17203a; m pd17p204 and m pd17204. for the cpu functions and internal hardware peripherals of the m pd17203a and m pd17p204, therefore, refer to the data sheet of the m pd17203a and m pd17204. product item program memory pull-up resistor of reset pin pull-up resistor of p0a and p0b pins main clock oscillator circuit subclock oscillator circuit v pp pin, prom program pins power supply voltage (t a = C20 to 75 c) package ? one-time prom ? 0000h-0fffh ? 4096x16 bits not provided provided not provided ? mask rom ? 0000h-0fffh ? 4096x16 bits on request (mask option) not provided v dd = 2.2 to 5.5 v (at 4mhz) m pd17p203a-001 m pd17p203a-002 m pd17p203a-003 m pd17203a provided not provided provided provided v dd = 2.9 to 5.5 v (at 4mhz) note 52-pin plastic qfp product item program memory pull-up resistor of reset pin pull-up resistor of p0a and p0b pins main clock oscillator circuit subclock oscillator circuit v pp pin, prom program pins power supply (t a = C20 to 75 c) package ? one-time prom ? 0000h-1effh ? 7936x16 bits not provided provided not provided ? mask rom ? 0000h-1effh ? 7936x16 bits on request (mask option) not provided v dd = 2.2 to 5.5 v (at 4mhz) m pd17p204-001 m pd17p204-002 m pd17p204-003 m pd17204 provided not provided provided provided v dd = 2.9 to 5.5 v (at 4mhz) note 52-pin plastic qfp note for details on the power supply voltage, refer to 4. elecrical specifications .
15 m pd17p203a, 17p204 3. one-time prom (program memory) writing, reading, and verification the program memory of 4096 x 16 bits ( m pd17p203a) and 7936 x 16 bits ( m pd17p204) one-time prom are provided. the following table lists the pins to be used for this prom writing, reading or verification. in prom mode, no address input pin is used. instead, the address is updated by the clock for input from the clk pin. 3.1 operation mode for writing, reading, and verification of program memory if +6 v is applied to the v dd and +12.5 v to the v pp pin after m pd17p204 has been placed in the reset status for a fixed time (v dd = 5v, reset = 0v), m pd17p204 enters program memory write, read, or verify mode. the md0 to md3 pins are used to set the operation modes listed in the following table. leave the pins not used for program memory writing, reading, or verification open or ground through pull-down resistors. function applies program voltage. inputs address update clock. selects operation mode. inputs and outputs 8-bit data. pin name v pp clk md0-md3 d0-d7 operating mode specification x: l or h md0 md1 md2 md3 hlhl lhhh llhh hxhh v dd +6 v v pp +12.5 v operating mode program memory address 0 clear mode write mode read/verify mode program inhibit mode
m pd17p203a, 17p204 16 3.2 program memory write procedure the program memory write procedure is as follows. high-speed program memory write is possible. (1) ground the unused pins through pull-down resistors. the clk pin must be low. (2) supply 5 v to the v dd pin. the v pp pin must be low. (3) after waiting for 10 microseconds, supply 5 v to the v pp pin. (4) operate the md0 to md3 pins to set program memory address 0 clear mode. (5) supply 6 v to the v dd pin and 12.5 v to the v pp pin. (6) set program inhibit mode. (7) write data in 1-millisecond write mode. (8) set program inhibit mode. (9) set verify mode. if data has been written connectly, proceed to step (10). if data has not yet been written, repeat steps (7) to (9). (10) write additional data for (the number of times data was written (x) in steps (7) to (9)) times 1 milliseconds. (11) set program inhibit mode. (12) supply a pulse to the clk pin four times to update the program memory address by 1. (13) repeat steps (7) to (12) to the last address. (14) set program memory address 0 clear mode. (15) change the voltages of v dd and v pp pins to 5 v. (16) turn off the power supply. steps (2) to (12) are illustrated below. reset v pp v dd gnd v dd +1 v dd gnd clk d0-d7 md0 md1 md2 md3 v pp v dd hi-z hi-z hi-z hi-z data input data output data input write verify additional data write address increment x-time repetition
17 m pd17p203a, 17p204 3.3 program memory read procedure (1) ground the unused pins through pull-down resistors. the clk pin must be low. (2) supply 5 v to the v dd pin. the v pp pin must be low. (3) after waiting for 10 microseconds, supply 5 v to the v pp pin. (4) operate the md0 to md3 pins to set program memory address 0 clear mode. (5) supply 6 v to the v dd pin and 12.5 v to the v pp pin. (6) set program inhibit mode. (7) set verify mode. data of each address is sequentially output each time a clock pulse is input to the clk pin four times. (8) set program inhibit mode. (9) set program memory address 0 clear mode. (10) change the voltages of v dd and v pp pins to 5 v. (11) turn off the power supply. steps (2) to (9) are illustrated below. v pp v dd gnd v dd +1 v dd gnd clk d0-d7 md0 md1 md2 md3 v pp v dd data output data output hi-z hi-z ? 1 cycle
m pd17p203a, 17p204 18 4. electrical specifications absolute maximum ratings (t a = 25 c) supply voltage input voltage high-level output current low-level output current operating ambient temperature storage temperature v dd v i i oh1 i oh2 i oh3 i oh4 i oh5 i oh6 i ol1 i ol2 i ol3 i ol4 t a t stg item symbol conditions ratings unit v v ma ma ma ma ma ma ma ma ma ma c c rem pin 1 pin (except for rem pin) total (except for rem pin) 1 pin total C0.3 to +7.0 C0.3 to v dd + 0.3 C30 C20 C7.5 C5.0 C22.5 C15.0 7.5 5.0 30 20 C20 to +75 C40 to +125 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? peak value effective value note peak value effective value note peak value effective value note peak value effective value note peak value effective value note note effective value = peak value x ? duty caution even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. the absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. be sure not to exceed or fall below this value when using the product. item symbol conditions min. typ. max. unit when the system clock is f x = 4 mhz, t a = C20 to 55 c when the system clock is f x = 4 mhz when the system clock is f x = 6 mhz, t a = C20 to 50 c when the system clock is fxt = 32 khz v dd1 v dd2 v dd3 v dd4 f x f xt 2.7 3.0 5.5 v 2.9 3.0 5.5 v 4.75 5.0 5.5 v 2.0 3.0 5.5 v 1.0 4.0 8.0 mhz 32.768 khz recommended operating range (t a = C20 to +75?c) supply voltage main clock oscillation frequency subclock oscillation frequency capacitance (t a = 25 c, v dd = 0 v) item symbol conditions min. typ. max. unit int, reset pins other than int, reset pins input capacitance c in c pin 10 pf 10 pf
19 m pd17p203a, 17p204 dc characteristics (v dd = v xram = 3 v, t a = C20 to +75 c, f x = 4 mhz, f xt = 32 khz) item symbol conditions min. typ. max. unit v ih = 3 v v ih = 3 v v ih = 3 v v ih = 3 v v ih = 3 v v il = 0 v v il = 0 v v il = 0 v, w/o pull-up resistors v il = 0 v, w/pull-up resistors v il = 0 v, w/o pull-up resistors v il = 0 v, w/pull-up resistors v il = 0 v v il = 0 v, w/o pull-up resistors v il = 0 v, w/pull-up resistors v oh = 2.7 v v oh = 2.7 v v oh = 1 v v oh = 2.7 v v oh = 2.7 v v ol = 0.3 v v ol = 0.3 v v ol = 0.3 v v ol = 0.3 v v ol = 0.3 v v ol = 0.3 v int tm0in reset p0a-p0d p1a-p1c int tm0in reset p0a,p0b p0c,p0d p1a-p1c p0a,p0b p1c rem led cmpout p0a,p0b,p1c p0c,p0d,p1b p1a rem led,wdout cmpout c = 0.1 m f, r = 82 k w operation mode halt mode generates both xt and x generates xt only generates both xt and x generates xt only operation mode, v xram = 3 v halt mode, v xram = 3 v, t a = 25 c 2.4 3.0 v 2.1 3.0 v 0 0.6 v 0 0.9 v 0.2 m a 0.2 m a 0.2 m a 0.2 m a 0.2 m a C0.2 m a C0.2 m a C0.2 m a C30 C60 C120 m a C0.2 m a C8 C15 C30 m a C0.2 m a C0.2 m a C30 C60 C120 m a C0.6 C2.0 C4.0 ma C0.6 C2.0 C4.0 ma C7.0 C15.0 C25.0 ma C0.3 C1.0 C2.0 ma C0.3 C1.0 C2.0 ma 0.5 1.5 2.5 ma 0.5 1.5 2.5 ma 1.5 4.5 7.5 ma 0.5 1.5 2.5 ma 0.5 1.5 2.5 ma 0.5 1.5 2.5 ma 0.8 1.1 1.6 v 0.5 2.0 4.0 ma 400 600 m a 2.0 ma 20 30 m a 3.0 5.0 7.0 m a 0.2 1.0 m a high-level input voltage low-level input voltage high-level input current low-level input current high-level output current low-level output current v ref output voltage supply current xram supply current v ih1 v ih2 v il1 v il2 i ih1 i ih2 i ih3 i ih4 i ih5 i il1 i il2 i il3 i il4 i il5 i il6 i il7 i il8 i il9 i oh1 i oh2 i oh3 i oh4 i oh5 i ol1 i ol2 i ol3 i ol4 i ol5 i ol6 v ref i dd1 i dd2 i dd3 i dd4 i xram1 i xram2 reset, int pins other than reset, int pins reset, int pins other than reset, int pins h
m pd17p203a, 17p204 20 xram low supply voltage data holding characteristics (t a = C20 to +75 c, v dd v xramdr ) item symbol conditions min. typ. max. unit 1.3 5.5 v v xramdr dc programming characteristics ( t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v) item symbol conditions min. typ. max. unit 0.7 v dd v dd v v dd C0.5 v dd v 0 0.3 v dd v 0 0.4 v 10 m a v dd C1.0 v 0.4 v 30 ma 30 ma data holding voltage other than clk clk other than clk clk v in = v il or v ih i oh = C1 ma i ol = 1.6 ma md0 = v il , md1 = v ih v ih1 v ih2 v il1 v il2 i li v oh v ol i dd i pp high-level input voltage low-level input voltage input leakage current high-level output voltage low-level output voltage v dd supply current v pp supply current cautions 1. v pp must not exceed +13.5 v, including the overshoot. 2. apply v dd before v pp and disconnect it after v pp .
21 m pd17p203a, 17p204 ac programming characteristics (t a = 25 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v) item symbol note 1 conditions min. typ. max. unit notes 1. these symbols are the corresponding m pd27c256 (maintenance product) symbols. 2. the internal address is incremented by 1 at the third falling edge of clk (with four clocks constituting as one cycle). the internal address is not connected to any pin. t as t as t m1s t oes t ds t ds t ah t ah t dh t dh t df t df t vps t vps t vds t vcs t pw t pw t opw t opw t mos t ces t dv t dv t m1h t oeh t m1r t or t pcr C t xh ,t xl C f x C t i C t m3s C t m3h C t m3sr C t dad t acc t had t oh t m3hr C t dfr C t res md0 = md1 = v il t m1h + t m1r 3 50 m s when data is read from program memory when data is read from program memory when data is read from program memory when data is read from program memory when data is read from program memory 2 m s 2 m s 2 m s 2 m s 2 m s 0 130 ns 2 m s 2 m s 0.95 1.0 1.05 ms 0.95 21.0 ms 2 m s 1 m s 2 m s 2 m s 10 m s 0.125 m s 4.19 mhz 2 m s 2 m s 2 m s 2 m s 2 m s 0 130 ns 2 m s 2 m s 10 m s address setup time note 2 (vs.md0 ) md1 setup time (vs. md0 ) data setup time (vs. md0 ) address hold time note 2 (vs.md0 - ) data hold time (vs. md0 - ) md0 -? data output float delay time v pp setup time (vs. md3 - ) v dd setup time (vs. md3 - ) initial program pulse width additional program pulse width md0 setup time (vs. md1 - ) md0 ? data output delay time md1 hold time (vs. md0 - ) md1 recovery time (vs. md0 ) program counter reset time clk input high-/low- level width clk input frequency initial mode set time md3 setup time (vs. md1 - ) md3 hold time (vs. md1 ) md3 setup time (vs. md0 ) address note 2 ? data output delay time address note 2 ? data output hold time md3 hold time (vs. md0 - ) md3 ? data output float delay time reset setup time
m pd17p203a, 17p204 22 program memory write timing program memory read timing v pp v dd gnd v dd +1 v dd gnd clk d0-d7 md0 md1 md2 md3 v pp v dd data input data output data input data input t res t vps t vds hi-z hi-z hi-z t 1 t ds t dh t dh t dv t df t ds t ah t as t opw t m0s t m1r t pw t pcr t m1s t m1h t m3s t m3h hi-z v pp v dd gnd v dd +1 v dd gnd clk d0-d7 md0 md1 md2 md3 v pp v dd t res t vps t vds hi-z hi-z t 1 t dv t xh t xl t had t dad data output data output t dfr t m3hr ? t pcr t m3sr t xh hi-z t xl
23 m pd17p203a, 17p204 5. package drawings 52 pin plastic qfp ( 14) item millimeters inches d f g k i j 1.0 1.0 1.60.2 1.0 (t.p.) 0.20 17.20.2 q 0.6770.008 0.039 0.039 0.0630.008 0.008 0.039 (t.p.) s52gc-100-3bh-2 a b f note each lead centerline is located within 0.20 mm (0.008 inch) of its true position (t.p.) at maximum material condition. c 14.00.2 0.551 m 0.15 0.006 0.1250.075 0.0050.003 +0.004 C0.003 +0.009 C0.008 a 17.20.2 0.6770.008 h 0.400.10 0.016 +0.004 C0.005 l 0.80.2 0.031 +0.009 C0.008 n 0.10 0.004 p 2.7 0.106 s r 3.0 max. 5 5 0.119 max. 5 5 +0.10 e0.05 b 14.00.2 0.551 +0.009 e0.008 m 39 40 27 26 14 13 1 52 c d g i h j k l m n p detail of lead end q s r h
m pd17p203a, 17p204 24 6. recommended soldering conditions soldering must be performed under the following conditions. for details of recommended conditions for surface mounting, refer to information document semiconductor device mounting technology manual (iei-1207). for other soldering methods, please consult with nec personnel. table 6-1. soldering conditions of surface mount type m pd17p203agc-001-3bh : 52-pin plastic qfp (14 14 mm) m pd17p203agc-002-3bh : 52-pin plastic qfp (14 14 mm) m pd17p203agc-003-3bh : 52-pin plastic qfp (14 14 mm) m pd17p204gc-001-3bh : 52-pin plastic qfp (14 14 mm) m pd17p204gc-002-3bh : 52-pin plastic qfp (14 14 mm) m pd17p204gc-003-3bh : 52-pin plastic qfp (14 14 mm) soldering method soldering conditions symbol package peak temperature: 235?c, time: 30 seconds max. (210?c min), number of times: 2 max., days: 7 days note (after that, prebaking is necessary for 20 hours at 125?c) infrared reflow ir35-207-2 (1) start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) do not clean flux with water after first reflow. package peak temperature: 215?c, time: 40 seconds max. (200?c min), number of times: 2 max., days: 7 days note (after that, prebaking is necessary for 20 hours at 125?c) vps vp15-207-2 (1) start second reflow after device temperature (which has risen because of first reflow) has returned to room temperature. (2) do not clean flux with water after first reflow. pin part heating pin temperature: 300?c max., time: 3 seconds max. (per side of device) note the number of days the device can be stored after the dry pack was opened, under storage conditions of 25?c and 65% rh max. caution do not use two or more soldering methods in combination (except the pin partial heating method). h
25 m pd17p203a, 17p204 appendix a. microcontrollers for learning remote controller product item 336 x 4 bits 4096 x 4 bits 2048 x 4 bits provided provided 28 1 m pd17204 7936 x 16 bits (mask rom) m pd17p203a 4096 x 16 bits (one-time prom) m pd17203a 4096 x 16 bits (mask rom) rom capacity ram capacity static ram capacity carrier generator for infrared remote controller receiver preamplifier for infrared remote controller i/o ports external interrupt (int) timer watchdog timer serial interface stack standby function 8-bit timer: 3 channels 4 channels watch timer: 1 channel provided (wdout output) 1 channel 5 levels (interrupt nesting: 3 levels) 7 levels (interrupt nesting: 3 levels) stop and halt modes 4 m s at 4 mhz (v dd = 2.2 to 5.5v) (v dd = 2.9 to 5.5v note ) (v dd = 2.2 to 5.5v) (v dd = 2.9 to 5.5v note ) 488 m s at 32.768 khz (v dd = 2.0 to 5.5 v) 52-pin plastic qfp package main system clock sub-system clock note the supply voltage varies depending on the operating ambient temperature. for details, refer to 4. electrical specifications. m pd17p204 7936 x 16 bits (one-time prom) instruction execution time (supply voltage) t a = C20 to +75 c
m pd17p203a, 17p204 26 appendix b. development tools the following tools are readily available for m pd17p203a and m pd17p204 program development. hardware name outline the ie-17k, ie-17k-et, and emu-17 are in-circuit emulators that can be commonly used with the 17k series products. the ie-17k and ie-17k-et are connected to the host machine, which is a pc-9800 in-circuit emulators series product or ibm pc/at tm , via rs-232-c. the emu-17k is inserted into an ie-17k expansion slot of a pc-9800 series product. ie-17k-et note 1 when these in-circuit emulators are used in combination with a system evaluation emu-17k note 2 board (se board) dedicated to each model of the device, they operate as the emulator dedicated to that model. a more sophisticated debugging environment can be created by using the man-machine interface software, simplehost tm . the emu-17k has a function that allows you to check the contents of the data memory real-time. the se-17204 is an se board for the m pd17203a, 17p203a, 17204 and 17p204. se board (se-17204) it may be used alone to evaluated a system, or in combination with an in-circuit emulator for debugging. the ep-17203gc is an emulation probe for the m pd17203a, 17p203a, 17204 and emulation probe 17p204. it connects an se board and the user system. when used with the (ep-17203gc) ev-9200g-52 this probe connects the se board and the target system. conversion socket the ev-9200g-52 connects the ep-17203gc and the target system. (ev-9200g-52 note 3 ) prom programmer the af9703, af9704, af9705, and af9706 are prom programmers that can (af-9703 note 4 , af-9704 note 4 program the m pd17p203a and 17p204. when connected with programmer adapter af-9705 note 4 , af9706 note 4 ) af-9808a, this prom programmer can program the m pd17p203a and 17p204. program adapter the af-9808a is an adapter for programming the m pd17p203agc and 17p204gc (af-9808b note 4 ) and is used in combination with the af-9703, af-9704, af-9705, and af-9706. notes 1. low-cost model: external power supply type 2. this is a product from i.c., corp. for details, consult i.c. 3. one ev-9200g-52 is supplied with the ep-17203gc. five ev-9200g-52s are optionally available as a set. 4. these are products from ando electric. for details, consult ando electric. h
27 m pd17p203a, 17p204 software outline machine as17k is an assembler that can be used in common with the 17k series products. when developing the program of the m pd17p203a and 17p204, as17k is used in combination with a device file (as17203, as17204). as17203 is a device file for m pd17203a, and 17p203a, and it is used in combination with an assembler commonly used for the 17k series (as17k). as17204 is a device file for m pd17204 and 17p204, and it is used in combination with an assembler for the 17k series (as17k). simplehost is a software package that enables man- machine interface on the windows tm when a program is developed by using an in- circuit emulator and a personal computer. name 17k series assembler (as17k) device file (as17203) device file (as17204) support software (simplehost) host pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at pc-9800 series ibm pc/at os media ms-dos tm pc dos tm ms-dos pc dos ms-dos pc dos ms-dos pc dos supply 5 2dh 3.5 2hd 5 2hc 3.5 2hc 5 2hd 3.5 2hd 5 2hc 3.5 2hc 5 2hd 3.5 2hd 5 2hc 3.5 2hc 5 2hd 3.5 2hd 5 2hc 3.5 2hc windows order code m s5a10as17k m s5a13as17k m s7b10as17k m s7b13as17k m s5a10as17203 m s5a13as17203 m s7b10as17203 m s7b13as17203 m s5a10as17204 m s5a13as17204 m s7b10as17204 m s7b13as17204 m s5a10ie17k m s5a13ie17k m s7b10ie17k m s7b13ie17k remark the corresponding os versions are as follows: os version ms-dos ver. 3.30 to ver. 5.00a note pc dos ver. 3.1 to ver. 5.0 note windows ver. 3.0 to ver. 3.1 note ver. 5.00/5.00a of ms-dos and ver. 5.0 of pc dos have a task swap function, but this function cannot be used with this software.
m pd17p203a, 17p204 28 [memo]
29 m pd17p203a, 17p204 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immedi- ately after power-on for devices having reset function.
no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: standard, special, and specific. the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices in standard unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 94.11 the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re- export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. simplehost is a trademark of nec corporation. ms-dos and windows are trademarks of microsoft corporation. pc/at and pc dos are trademarks of ibm corporation. [memo] m pd17p203a, 17p204

▲Up To Search▲

Price & Availability of UPD17P203AGC-001-3BH

	To Download UPD17P203AGC-001-3BH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .